1. Field of the Invention
The present invention is directed toward the field of memory, and more particularly to a first-in-first-out (FIFO) memory device that includes programmable cell sizes and multiplexing among FIFO memory cores.
2. Art Background
There are many types of memory devices that are used to store data. One type of memory device is known as a first-in-first-out (FIFO) memory or buffer. In a FIFO memory, data is stored in a sequential order as data is written to the device. Typically, FIFO devices maintain a write pointer that specifies the location or address to write the next data entry into the FIFO. For each write operation, the write pointer is incremented. The FIFO memory is sequentially read in the same order as it was written. Typically, to implement a read operation, a read pointer is maintained, and the read pointer is incremented for each subsequent read operation. Thus, the data that is first written to the FIFO device is also the data that is first read from the FIFO device.
FIFO memories have many uses in circuit applications. For example, FIFOs may be used as a queue for storing packets of data in a network device. For the network application, data packets are stored in the FIFO in the sequential order that they are written. For routing or distribution, the data packets are sequentially read starting with the first data packets written.
A specification, known as the universal test and operation physical (PHY) interface for asynchronous transfer mode (ATM) or the UTOPIA specification, defines an interface between the ATM physical media layer and the ATM layer itself. As set forth in the UTOPIA specification, the storage of data in the FIFO device may be arranged in cells. In this configuration, sequential write operations are executed to fill an entire cell with data. Similarly, sequential read operations are executed on a cell to read all data stored in that cell. The UTOPIA specification specifies a cell size of 53 bytes per cell. Although the 53 bytes per cell may be suited for certain applications, other applications, such as different network standards that use different packet sizes, may be suited for different cell sizes. The ability to select the number of bytes per cell provides a more flexible FIFO device that may be suited for more applications. For example, a device may be configured to permit the selection of a wide range of cell sizes. Consequently, it is desirable to develop a FIFO memory that permits a user to specify a cell size by selecting the number of bytes for each cell.
A variable cell size circuit supports user programmable cell sizes in a memory device. The variable cell size circuit includes a counter and a comparator, and it controls successive accesses to a cell in the memory device. The comparator receives a cell size value that specifies the number of bytes for the current cell. The counter generates a count that specifies a number of accesses to the cell, and the comparator compares the count with the cell size value. In addition, the comparator resets the counter when the count equals the cell size value to initialize the circuit for a subsequent access operation. In one embodiment, the memory comprises a first-in-first-out (FIFO) memory, and the access operations include read and write operations to the cell. The variable cell size circuit further includes a prediction circuit that indicates completion of access to the cell a predetermined number of counts prior to completion of the actual access.
In one embodiment, the FIFO memory device supports a one byte write operation and a two byte read operation. For this embodiment, an alignment circuit generates data for write operations in cells that store an odd number of bytes per sell to compensate or align for the two byte per cell read operations. Specifically, the alignment circuit programs predetermined data into an additional byte position, during a byte insertion operation, and it programs over a previously written byte position in a byte deletion operation.
In one embodiment, the first-in-first-out (FIFO) memory device includes a plurality of FIFO memory cores that contain a plurality of cells. Each FIFO memory core includes a circuit that generates a cell available signal to indicate whether a cell in a corresponding FIFO memory core is available for reading. An arbiter receives the cell available signals, and it generates control signals to select one of the FIFO memory cores. An output selection circuit utilizes the control signals to output data from one of the FIFO memory cores. In one embodiment, the arbiter contains a round robin sequencer for selecting a FIFO memory core with a cell available in a sequential order. The FIFO memory device further includes a plurality of output pins that receive the cell available signals and that receive a prediction signal. Thus, the cell available information and the prediction signal are output externally from the FIFO device.